1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to high density, high performance memory integrated circuits, such as read-only-memory (ROM) or electrically programmable read-only-memory (EPROM).
2. Description of Related Art
With goals toward increased performance and higher density, various integrated circuit design approaches are known for memory devices such as ROM, EPROM, and other types including electrically-erasable programmable read-only-memory (EEPROM) and flash memory.
One advantageous design uses a so-called "flat" cell design approach. For example, flat cell ROM designs are well documented. One example of a ROM implementation using flat cell design is disclosed in U.S. Pat. No. 5,117,389, issued to inventor Tom D. H. Yiu on May 26, 1992, and entitled "Flat-Cell Read-Only-Memory Integrated Circuit." Other flat cell memory devices are shown in U.S. Pat. No. 5,241,497 (issued to James A. Komarek on Aug. 31, 1993 and entitled, "VLSI Memory with Increased Memory Access Speed, Increased Memory Cell Density and Decreased Parasitic Capacitance"), and U.S. Pat. No. 4,990,999 (issued to Motohiro Oishi et al. on Feb. 5, 1991 and entitled, "Semiconductor Memory Device Using High-Density and High-Speed MOS Elements").
Typically, a ROM array is implemented with a plurality of metal-oxide-semiconductor (MOS) transistors, or memory cells, arranged as an array of bitlines and wordlines. A single memory cell stores a bit of data.
Each MOS device or memory cell can be turned on (i.e. allow electrical current to conduct between the source and the drain) by applying a voltage V.sub.GS to its gate that is higher than its threshold voltage. If the applied voltage V.sub.GS is lower than the threshold voltage, the MOS device is not turned on. To program code in a memory cell in a ROM array during the manufacturing process, various code programming techniques such as ion implantation with masks, are employed. Based on the overall circuitry, ion implantation can either raise or lower the threshold voltage, thus storing either a "0" or "1".
While the flat-cell design approach achieves substantial density and performance, improvements are still desirable. For example, in U.S. Pat. No. 5,241,497 (Komarek), the block or bank select transistors are placed in a location in the substrate that increases the vertical pitch of the integrated circuit layout. Additional metal-to-diffusion region contacts are also provided specifically for the virtual ground connections which take up additional space on the integrated circuit by increasing its vertical pitch.
Additionally, horizontal pitch may also be improved. In U.S. Pat. No. 4,990,999 (Oishi), metal wiring lines are provided over the main diffusion bitlines and metal contacts are provided for each metal wiring line coupling it to the main diffusion lines. Based on the horizontal placement of these metal contacts, cell sizes, and hence the density of the integrated circuit, appear to be somewhat limited.
Accordingly, a need exists in the integrated circuit industry for increasing performance and density of an integrated circuit memory array by effectively utilizing existing resources without complicating the fabrication process. With complex processes, control of critical dimension decreases. Employing a simple fabrication process should result in a higher yield for the integrated circuit.